My name is Benny Akesson and I am currently working as Research Fellow at Embedded Systems Innovation by TNO in the Netherlands. My research is in the area of Real-Time Embedded Systems with interests in resource arbitration, performance virtualization and analysis, power estimation, variability, and design automation.
|Short biography (<50 words)||Long biography (<200 words)|
|2017-02-15 - Paper Accepted at RTAS|
|A paper entitled "Partitioning and Analysis of the Network-on-Chip on a COTS Many-Core Platform" was recently accepted for publication at RTAS. This paper was a collaboration with former colleagues at the CISTER Research Unit, as well as friends from MDH in Sweden. The paper addresses the issue of interference between applications in many-core platforms interconnected using rate-regulated Networks-on-Chip (NoC), such as the Kalray MPPA. The main contributions of the paper are 1) a partitioning strategy for reducing contention on the NoC, 2) an analysis technique to determine the Worst-Case Traversal Time of packages under the proposed strategy, and 3) a method to determine parameters for the NoCs rate regulators to get minimal WCTT and ensure that buffers never overflow. The benefits of the proposed approach is evaluated both using simulation and by experiments on a Kalray MPPA. Furthermore, an industrial case study from the automotive domain shows the tightness of the proposed analysis.|
|2016-09-26 - Yonghui Li Defends Dissertation|
Today, we celebrate that Yonghui Li successfully defended his PhD dissertation "Design and Formal Analysis of Real-Time Memory Controllers" and became Dr. Li.
The thesis defines a dynamically scheduled real-time memory controller architecture, which is implemented as a SystemC simulation model. It then continues by analyzing
the worst-case response time and minimum guaranteed bandwidth using three different formal frameworks. The first framework is a mathematical formulation of both the actual and worst-case timing behavior as a set of equations and proofs of their correctness. These equations are also implemented in an open-source tool. The drawback of this kind of mathematical formulation is that it takes a long time to derive and prove correct. The second analysis approach addresses this by shifting the effort of the user from performance analysis to modeling the memory controller as a mode-controlled data-flow graph, which can be analyzed with existing tools. This approach is faster, but only bounds the minimum guaranteed bandwidth and not the worst-case response time. This limitation is overcome by the final approach, which is to model the memory controller using timed automata and bound its worst-case performance using a model checker. So, in summary, one controller architecture and three approaches to analyse its worst-case performance. This work hence gives unique insight into the strengths and weaknesses of different modeling and analysis approaches in terms of accuracy, expressiveness, memory consumption, and computation time.
The defense itself was well-prepared and confident and the committee seemed to really like the work. I am also really pleased with how it came out and I would like to thank Yonghui for the years of hard work that went into creating it. It was a pleasure to work with you during these years and I wish you all the best in your future career.
|2016-07-08 - Outstanding Paper Award at ECRTS|
|I am pleased to announce that our paper "Cache-Persistence-Aware Response-Time Analysis for Fixed-Priority Preemptive Systems" got an Outstanding Paper Award at the Euromicro Conference on Real-Time Systems (ECRTS) in Toulouse. We are glad that the work was well-received and hope that the community will enjoy reading the paper.|
|2016-06-21 - Article Accepted in IEEE Transactions on Computers|
Manil Dev Gomony just had a journal article entitled "A Globally Arbitrated Memory Tree for Mixed-Time-Criticality Systems" accepted in the high-impact journal IEEE Transactions on Computers. This article extends a conference paper published at DATE in 2015 that was called
"A Generic, Scalable and Globally Arbitrated Memory Tree for Shared DRAM Access in Real-Time Systems" that was published in collaboration with Jamie Garside and Neil Audsley from University of York. The original paper explained the design and efficient hardware implementation of a transaction arbiter for real-time systems that could be configured to behave like any of five well-known arbiters, i.e. TDM, Round Robin, Credit-Controlled Static Priority, Priority-Based Scheduler, and Frame-Based Static Priority. The key feature of the arbiter is that it is distributed, which means that accounting and enforcement is not
done in a single centralized location, allowing it to scale to systems with many resource clients without negatively impacting the maximum frequency at which it operates.
The journal article extends the original conference paper by adding more detail and examples on the design of the memory tree, as well as improving positioning. However, it also extends the scope of the work to consider more complex Mixed-Time-Criticality systems where some clients are more concerned about average-case than worst-case performance. It also considers that the requirements of the clients may be diverse, i.e. that some may have high bandwidth requirements and are latency-tolerant, while others have low bandwidth requirements, but are latency-critical. This is diversity of requirements is addressed by showing how the memory tree supports the transaction arbiter to be chosen individually per client rather than once for the entire system. For example, some real-time clients may be configured by non-work-conserving TDM arbitration to get predictable bandwidth and latency while enjoying complete temporal isolation from other clients, which simplifies integration and certification. Other clients sharing the same resource, may be scheduled using e.g. using a work-conserving Frame-Based Static Priority scheduler to reflect an interest in low average latency while still distinguishing their relative latency-sensitivity. The memory tree supports any combination of the mechanisms discussed above, but we provide a formal analysis of the mixed arbitration algorithm explained above. The article demonstrates the benefits of this approach on a VHDL hardware implementation, as well as its cost in terms of area and power compared to centralized non-mixed arbitration policies by means of ASIC synthesis.
|2016-06-14 - Journal Article Accepted in ACM TODAES|
We just received the good news that Hazem's article "
Reducing the Complexity of Dataflow Graphs using Slack-based Merging" has been accepted for publication in
ACM Transactions on Design Automation of Electronic Systems (TODAES). The article addresses an important problem when working with synchronous data-flow (SDF)
graphs, namely that the size of the graph explodes when transforming it to its equivalent homogeneous (HSDF) representation, which prevents any design or analysis
algorithms requiring this transformation as a first step from scaling to larger graphs. In the scope of Hazem's work, this has caused problems when converting an SDF
graph into a set of independent periodic real-time tasks.
This article proposes a heuristic algorithm to reduce the size of the resulting HSDF graph prior to analysis by merging actors in the graph, thereby speeding up analysis algorithms using the resulting graph. Three key properties of the algorithm are: 1) it cannot violate the latency or throughput requirements of the original graph, 2) it cannot cause deadlock in the resulting merged graph, and 3) only HSDF actors corresponding to firings of the same SDF actor can be merged to enable the resulting merged graph to be efficiently used by mapping algorithms. The behavior of the algorithm is evaluated with applications from the SDF3 benchmark suite and it is compared to results of an optimal exhaustive merging algorithm for smaller graphs.
|2016-04-22 - Two Papers Accepted at ECRTS 2016!|
Two papers have been accepted for presentation at the 28th Euromicro Conference on Real-Time Systems (ECRTS 2016) in Toulouse, France.
The first paper is entitled "Cache-Persistence-Aware Response-Time Analysis for Fixed-Priority Preemptive Systems" as is a collaboration
with Syed Aftab Rashid, Geoffrey Nelissen, and Eduardo Tovar from CISTER and Damien Hardy and Isabelle Puaut from University of Rennes.
This paper presents a WCRT analysis for single-core fixed-priority preemptive systems that exploits persistent cache blocks that are known
to be in the cache to reduce WCRT.
The title of the second paper is "Contention-Free Execution of Automotive Applications on a Clustered Many-Core Platform" that was written together with Borislav Nikolic and Vincent Nelis from CISTER, Matthias Becker and Thomas Nolte from MRTC, and Dakshina Dasari from Bosch. This work presents a contention-free execution framework for automotive applications on many-core platforms, which combines privatization of memory banks together with defined access phases to shared memory resources. An Integer Linear Programming (ILP) formulation is presented to find the optimal time-triggered schedule for execution as well as for accesses to shared memory. Additionally, a heuristic solution is presented that generates the schedule in a fraction of the time required by the ILP.
|2016-04-03 - New Book Available for Pre-order|
Our new book "Memory Controllers for Mixed-Time-Criticality Systems: Architectures, Methodologies and Trade-offs" is now available for pre-order at Springer. The book is based on the excellent PhD thesis of Sven Goossens and discusses the design and FPGA implementation of a real-time memory controller for mixed-criticality systems. The controller can provide complete temporal isolation to its clients as well as hard bounds
on the worst-case response time of transactions and the bandwidth offered by the memory. In addition, it provides competitive average-case performance for soft real-time and best-effort applications using a conservative open-page policy. The design is highly configurable and the book carefully quantifies the trade-offs between bandwidth, response time, and power that this enables. To facilitate the discussion about power, the book also presents the power model that came out of the PhD dissertation of
Karthik Chandrasekar and gives an up-to-date description of the open-source DRAMPower tool that implements it.
Update: The contents of the book are now available on SpringerLink
|2016-03-01 - New Position at TNO-ESI|
Today, I started a new position as a Research Fellow at Embedded Systems Innovation by TNO (TNO-ESI) in Eindhoven.
TNO-ESI is a leading Dutch research group for high-tech embedded systems design and engineering. It has a close cooperation with high-tech industry, as well as a strong association with fundamental research of academia, both national and international. This means I am now transitioning to applied science in an industrial setting and I look forward
to the new challenges and opportunities that entails.
I want to thank the good people a CISTER for the time I have spent with the unit. I find it a very nice place to work with good researchers and a friendly atmosphere. I appreciate the intellectual freedom I had to pursue my ideas and interests, as well as the interesting collaborations and growth opportunities I got sucked into. I hope we will have the pleasure of working together again in the future.
|2015-12-14 - Paper Accepted at RTAS 2016|
|Yonghui Li is on a roll! Two months ago he received the best paper award at ESTIMEDIA for his work on modelling and analysis of a dynamically scheduled DRAM controller using mode-controlled data-flow graphs. Now, he just had a paper entitled "Modeling and Verification of Dynamic Command Scheduling for Real-Time Memory Controllers" that models and analyses the same memory controller using timed atomata. A key highlight of this work is that it quantitatively compares data-flow analysis, timed automata, and two other approaches from Yonghui's 2015 article in Real-Time Systems in terms of guaranteed bandwidth and worst-case execution time. This gives interesting insights into what these different approaches can and cannot model and what the impact of those limitations are on the performance guarantees. This work was the result of a fruitful collaboration with Kai Lampka from Uppsala University in Sweden.|
|2015-12-09 - Sven Goossens Successfully Defended Dissertation|
After successfully defending his dissertation "A Reconfigurable Mixed-Time-Criticality SDRAM Controller", Sven Goossens
earned himself a PhD degree and the right to call himself a doctor. The work proposes a pattern-based SDRAM controller targeting mixed-time-criticality systems, i.e.
systems where some memory clients need firm worst-case guarantees on bandwidth and latency, while other clients only care about average-case performance. A new memory controller
architecture is designed to address this mix of requirements and it is implemented both as a cycle-accurate SystemC simulation model and as synthesizable RTL code for generating
FPGA instances. A unique feature of this memory controller is its conservative open-page policy that leaves rows open in the memory banks as long as possible to exploit
locality and boost average-case performance, but closes them just in time to avoid reducing the worst-case performance.
The work also parameterizes the concept of memory patterns by allowing the number of banks and the number of bursts per bank to be chosen when the patterns are generated. This allows patterns with different degrees of bank-level parallelism to be created for six different generations of DRAM for any request size, enabling the user to make a trade-off between worst-case bandwidth, worst-case response time, and power consumption. To generate efficient memory patterns, the work proposes an integer linear programming formulation that provides optimal patterns, as well as a near-optimal heuristic that runs in a fraction of the time. In addition to generating predictable memory patterns that provide bounded bandwidth and execution times, composable read and write patterns can be generated with negligible performance loss. These patterns have equal length and can be used to provide complete temporal isolation between memory clients when combined with a non-work-conserving Time-Division Multiplexing (TDM) arbiter in the front-end. The memory patterns are generated offline at design time, but are programmed at run-time when the memory controller is initialized. Lastly, the proposed controller supports run-time reconfiguration of its TDM arbiter, allowing it to be safely reprogrammed when applications dynamically start and stop at run-time without sacrificing the worst-case guarantees of applications that keep running.
I would like to thank Sven for the five years of hard work. It has been a pleasure to work with such a versatile and independent young researcher who seems to be succesful at whatever he attempts, be it design, analysis, writing papers, or hardware/software implementation in more or lesss any language. He has also been an excellent member of the Memory Team and the larger CompSoC Team, never passing on an opportunity to use his skills to support other members of the team. At the end of January, Sven starts his new career with Intrinsic-ID in Eindhoven. We wish him the best of luck with his new job and hope to stay in touch.
|2015-11-12 - Article Accepted in Journal of Systems and Software|
Congratulations to Anna Minaeva for having her article "Scalable and Efficient Configuration of Time-Division Multiplexed Resources"
accepted in Journal of Systems and Software. The article is an extension of our conference paper "An Efficient Configuration Methodology for Time-Division Multiplexed Single Resources"
that was presented at the Real-Time and Embedded Technology and Applications Symposium (RTAS) earlier this year. The original conference paper addresses the problem of configuring
a Time-Division Multiplexing (TDM) arbiter that provides access to a single shared resource, such as a memory, in a way the satisfies the bandwidth and latency requirements of all memory clients. This is achieved
using an optimized Integer Linear Programming (ILP) formulation.
The newly accepted article extends the problem scope to consider more complex system with a larger number of memory clients and a longer TDM frame. For large problems, the previous ILP formulation takes unpractically long to solve, which is addressed by using it as a building block in a Branch and Price framework to improve its scalability. This approach decomposes the problem into smaller sub-problems and uses more sophisticated exploration methods to navigate the search-space, enabling the number of clients to be increased by up to a factor of 8 compared to the original ILP formulation.
|2015-11-11 - Hazem Ali in HiPEAC Newsletter|
|Last year, my PhD student Hazem Ali got a HiPEAC collaboration grant sponsoring a three month visit in the Electronic Systems group at Eindhoven University of Technology, hosted by Dr. Sander Stuijk. The topic of the joint research is related to the borderland between data-flow and traditional real-time analysis. On page 15 in the latest issue of the HiPEAC Newsletter, you can read more about his stay.|
|2015-10-09 - Yonghui Li Wins Best Paper Award at ESTIMEDIA|
|We won the Best Paper Award at the 13th IEEE Symposium on Embedded Systems for Real-Time Multimedia (ESTIMedia) for our paper "Mode-Controlled Data-Flow Modeling of Real-Time Memory Controllers". The paper was first-authored by Yonghui Li and was a successful collaboration with Orlando Moreira (previously with ST-Ericsson, currently with Intel) and two of his PhD students at Eindhoven University of Technology. We are happy that our work was well-received and hope the community will like the paper.|
|2015-09-07 - Manil Dev Gomony Successfully Defends PhD Thesis!|
Today, Manil Dev Gomony has successfully defended his PhD thesis entitled
"Scalable and Bandwidth-Efficient Memory Subsystem Design for Real-Time Systems". The thesis proposes an architecture
for a real-time memory subsystem that scales well in terms of area and maximum synthesizable frequency with an increasing number of memory clients. This subsystem architecture
comprises a memory interconnect called Globally Arbitrated Memory Tree (GAMT) a Multi-Channel Memory Controller (MCMC), as well as a technique to couple those components and have a single
point of arbitration for both resources. The thesis also proposes a design flow for automatically choosing the memory device, mapping clients to memory channel, and configure arbiters to satisfy client requirements.
Among Manil's achievements, we specifically highlight two achievements with respect to publishing. First of all, he had a paper accepted at the DATE conference every year during his PhD. Secondly, none of his publications were ever rejected anywhere. This shows that Manil managed to publish in competitive forums in his field and that his work was well-received. Currently, Manil works as a Researcher at Bell Laboratories of Alcatel-Lucent in Belgium. We wish him the best of luck in his future career!
|2015-08-14 - H2020 Project HERCULES in Grant Agreement Preparation|
The European Commission just notified us that our H2020 IA project HERCULES
(High-pErformance Real-time arChitectUres for Low-power Embedded Systems) has reached the
stage of grant agreement preparation. Earlier this year, I took the lead on this proposal on behalf of CTU Prague
and also contributed more generally to the preparation. Given the competitive nature of H2020, I am pleased to see
that the work was well received. A particular congratulations to Marko Bertogna and his team at University of Modena
for their hard work on coordinating this proposal. Now let's hope the negotiation phase goes well!
Project HERCULES has the ambitious goal to provide the required technological infrastructure to obtain an order-of-magnitude improvement in the cost and power consumption of next generation real-time applications. It will develop an integrated framework to allow achieving predictable performance on top of cutting-edge heterogeneous COTS multi-core platforms, implementing real-time scheduling techniques and execution models recently proposed in the research community. The framework will be applied to two innovative industrial use cases: a pioneering autonomous driving system for the automotive domain, and a visual recognition system for the avionic domain.
|2015-07-23 - Paper about Data-Flow Modeling of Memory Controllers at ESTIMEDIA|
Yonghui Li is having a good month. Last week he was notified that his journal article was accepted
by the Real-Time Systems journal. This week, his paper
"Mode-Controlled Data-Flow Modeling of Real-Time Memory Controllers" was accepted for presentation
at the 13th IEEE Symposium on Embedded Systems for Real-Time Multimedia (ESTIMedia), a symposium that is a part
of the Embedded Systems week in Amsterdam.
The paper is a collaboration with Orlando Moreira (previously with ST-Ericsson, currently with Intel) and his PhD students and continues Yonghui's work on design and analysis of dynamically scheduled memory controllers. This work presents a mode-controlled data-flow model of the memory controller, which is used to derive bounds on the worst-case bandwidth for requests with variable sizes. An important difference with Yonghui's earlier work is that this paper extends an existing model of computation to capture the memory controller and uses existing tools to do the analysis. This contrasts to his previous work where the analysis was done from scratch and required a lot of manual proofs. Examining this trade-off between modeling and analysis effort and quality of the results is a red thread through all of Yonghui's work and is expected to be the main topic of his thesis.
|2015-07-15 - Accepted Article about Dynamic Command Scheduling in Real-Time Systems Journal|
Today, we congratulate Yonghui Li on his first accepted journal article. The article is entitled
"Architecture and Analysis of a Dynamically-Scheduled Real-Time Memory Controller" and has been
accepted in the Real-Time Systems journal. The work extends his paper
"Dynamic Command Scheduling for Real-Time Memory Controllers" that was presented at ECRTS 2014.
The previous conference paper introduced a back-end architecture and scheduling algorithm for a dynamically
scheduled SDRAM controller supporting variable transaction sizes and different degrees of bank interleaving. The properties
of the back-end was extensively analyzed and worst-case execution times (WCET) of scheduled transactions was derived using two different methods
with varying complexity and accuracy.
The newly accepted article extends this work by proposing a corresponding memory controller front-end, along with a complete response time analysis for memory transactions of variable sizes. A key feature of the front-end is that it features a non-work-conserving TDM arbiter, which provides static information about the order in which transactions of different sizes are scheduled, allowing the response time analysis to leverage the flexible WCET analysis of the back-end to provide tighter bounds. In addition, it is shown in which order memory clients with different request sizes should be served to minimize the total response time. The results demonstrate that dynamic command scheduling significantly outperforms our semi-static (pattern-based) approach in the average case, while it performs equally well or better in the worst-case with only a few exceptions.
|2015-07-13 - Article Accepted in IEEE Transactions on Computers|
|The spree of accepted journal articles continues as Sven Goossens' article entitled "Power/Performance Trade-offs in Real-Time SDRAM Command Scheduling" was accepted for publication in IEEE Transactions on Computers. The article contains a detailed discussion about the trade-offs between bandwidth, execution time, and power when DRAM requests are scheduled by a real-time memory controller under a close-page policy. The results cover a wide range of memories ranging from DDR2/3/4 to LPDDR1/2/3 for different request sizes and amounts of bank parallelism. Other key contributions of the article are: 1) publicly available heuristic and optimal algorithms for generation of memory patters that covers all aforementioned memories, 2) a simple abstraction that quickly captures the differences between the different DRAM generations allowing algorithms and analyses to be easily adapted to cover all of them, and 3) a pairwise bank-group interleaving scheme for DDR4 that exploits bank grouping for improved performance.|
|2015-07-01 - Temporary Contract with CISTER|
|My contract with Czech Technical University in Prague has run its course. However, the good people at the CISTER/INESC TEC research unit at the Polytechnic Institute of Porto, my former employer, was quick to offer me a temporary contract until a new long-term plan is in place. At my new job, I will continue my research on real-time embedded systems, just like before, as well as preparing project proposals to fund future research. I thank CISTER for the opportunity and look forward work with them again!|
|2015-06-18 - Article Accepted in Science of Computer Programming|
|The past two months have been very good to us with five journal articles being accepted in something resembling a ketchup-effect. The most recent addition is an article entitled "Certifying Execution Time in Multicores" that was accepted by the Elsevier journal Science of Computer Programming. In essence, this article is a summary of the PhD dissertation of Vitor Rodrigues, whom I collaborated with over the past years. My main contribution to this work is proposing the latency-rate model as an abstraction of the service provided by a shared resource, such as a memory. We incorporated this model into Vitors timing analysis tool based on abstract interpretation to enable scalable timing analysis of multi-core platforms with shared resources.|
|2015-05-24 - ACM TECS Accepts Another Journal Article|
ACM Transaction of Embedded Computing Systems (TECS) recently informed us
that our article "Maximizing the Number of Good Dies for Streaming Applications in NoC-based MPSoCs under Process Variation"
has been accepted for publication. This work nicely summarizes the
dissertation of Davit Mirzoyan from his
four year PhD studies at Delft University of Technology under the supervision of Kees Goossens and myself.
The article addresses design of real-time systems for streaming applications constrained by a throughput requirement with reduced design margins, referred to as better than worst-case design. The first contribution is a complete modeling framework that captures a streaming application mapped to a NoC-based multiprocessor system with voltage-frequency islands under process-induced die-to-die and within-die frequency variations. The framework is used to analyze the impact of variations in the frequency of hardware components on application throughput at the system level. The second contribution is a methodology to use the proposed framework and estimate the impact of reducing circuit design margins on the number of good dies that satisfy the throughput requirement of a real-time streaming application. It is shown on both synthetic and real applications that the proposed design approach can increase the number of good dies by up to 9.6% and 18.8% for designs with and without fixed SRAM and IO blocks, respectively.
|2015-05-16 - Article Accepted in Real-Time Systems Journal|
A journal article entitled "A Framework for Memory Contention
Analysis in Multi-Core Platforms" has been accepted for publication
in Real-Time Systems. This article is a collaboration with
Dakshina Dasari and Vincent Nelis and is a result from the time I spent with
the CISTER-ISEP Research Unit in Porto.
The article proposes a unified framework to bound memory interference in multi-core platforms for a variety of different arbiters, such as time-division multiplexing (TDM), fixed priority, and an unspecified work-conserving arbiter. Our framework clearly demarcates the arbiter-dependent and independent stages in the analysis of interference. The arbiter-dependent phase takes the arbiter and the task memory-traffic pattern as inputs and produces a model of the availability of the bus to a given task. Then, based on the availability of the bus, the arbiter-independent phase determines the worst-case request-release scenario that maximizes the interference experienced by the tasks due to memory contention. We experimentally evaluate the quality of the analysis by comparison with a state-of-the-art TDM analysis approach and consistently showing a considerable reduction in maximum interference.
|2015-05-07 - IEEE Senior Membership Awarded|
|I was just notified that my application for Senior Membership in the IEEE was granted and that I have been elevated to Senior Member. The notification states that "IEEE Senior Membership is an honor bestowed only to those who have made significant contributions to the profession", which is comforting appreciation of my work. I want to thank the IEEE Senior Members and Fellows that supported my application by giving their recommendations.|
|2015-05-06 - Two Articles Appeared in Journal of Systems Architecture|
Two articles that were submitted to a Journal of Systems Architecture
Special Issue on High-performance and Real-time Embedded Systems have now appeared online.
The first article is called "T-CREST: Time-predictable Multi-Core Architecture for Embedded Systems" and summarizes
the work done in the recently concluded FP7 STREP project T-CREST, where me and my students worked on time-predictable
The second article is entitled "Dataflow Formalisation of Real-Time Streaming Applications on a Composable and Predictable Multi-Processor SOC" and shows how data-flow graphs can be used to model streaming applications mapped to the CompSoc platform and predict its minimum throughput. The basic idea is to start from a data-flow graph of the application and add additional nodes and edges that capture the mapping and timing behavior of all hardware components software libraries, and schedulers in the system. The approach is verified by comparing the predicted performance to the actual performance of an application executing on a CompSoc instance on an FPGA. The article clearly demonstrates the potential of modeling systems in which the behavior of all hardware and software components are known.
|2015-03-17 - Invited Presentation at CMAS 2015.|
I have recently accepted an invitation to speak at the
First TCRTS Workshop on Certifiable Multicore Avionics Systems (CMAS), which takes place on April 13 and
is co-located with RTAS 2015 in
Seattle. The presentation is made in collaboration with Jan Nowotsch at Airbus Group Innovations, where I was
a Visiting Researcher during two months last year. The title of the presentation is
Towards Certifiable Resource Sharing in Safety-Critical Multi-Core Real-Time Systems and discusses current problems
and state-of-the-art methods for resource sharing in real-time multi-core platforms. The abstract of the presentation is found below:
The proliferation of multi-core platforms has had great impact on embedded computing. Multiple cores exploiting task-level parallelism offer performance far beyond what is possible with a single core, while staying within an acceptable power envelope. Since resources, such as interconnect and memories, are often shared between cores, the platforms have also become increasingly cost efficient. However, resource sharing results in interference between concurrently executing applications, which causes problems in real-time systems where such interference must be either bounded or completely eliminated. As a result, safety-critical systems, for example in the avionics domain, have not yet been able to capitalize on the benefits of multi-core platforms due to stringent certification requirements.
This presentation discusses the state-of-the-art in resource sharing in multi-core systems and its application to safety-critical real-time systems. First, a survey of efforts to build time-predictable resources, such as interconnects and memory controllers, is provided. Then, software-based interference mitigation mechanisms and analyses for these resources in commercial-of-the-shelf platforms are discussed. This is followed by an overview of the approach proposed by Airbus Group Innovations to manage interference and compute worst-case execution times of applications running on a Freescale P4080 multi-core platform. The presentation is concluded by highlighting open issues and future directions towards certifiable resource sharing in safety-critical multi-core real-time systems.
Update: The slides are available here.
|2015-02-05 - Paper Accepted at RTAS 2015|
We just had a paper accepted at the Real-Time and Embedded Technology and Applications Symposium (RTAS) in Seattle.
The paper is entitled "An Efficient Configuration Methodology for Time-Division Multiplexed Single Resources" and presents
an ILP-based methodology to allocate TDM slots to resource clients, such that bandwidth and latency constraints are satisfied while
resource utilization is minimized. A heuristic algorithm is furthermore proposed to determine the number of TDM slots in the schedule.
This paper is a collaboration both with colleagues here at CTU Prague and with Andrew Nelson from Eindhoven University of Technology.
For the camera-ready version of the paper, please click here.
|2014-12-11 - Back in Prague|
I am now back from my two month research visit at Airbus Group Innovations. During my stay, I primarily worked on two things:
|2014-11-02 - Paper Accepted at PDP 2015|
|Today, we congratulate Hazem Ali for having a paper accepted at PDP 2015. The paper is entitled "Generalized Extraction of Real-Time Parameters for Homogeneous Synchronous Dataflow Graphs" and proposes a heuristic methodology for extracting real-time parameters, such as periods, deadlines and offsets, for applications specified as homogeneous synchronous data-flow (HSDF) graphs. The benefit of the approach is that it enables HSDF applications to be analyzed using traditional real-time techniques and scheduled with common real-time schedulers, such as earliest-deadline first.|
|2014-10-30 - Memory Team has Two Papers Accepted at DATE 2015|
The notifications from the DATE conference are in and the Memory Team scores 2 out of 2, just
like in 2014. The first paper entitled "A Generic, Scalable and Globally Arbitrated Memory Tree for
Shared DRAM Access in Real-Time Systems" was first-authored by Manil and is a collaboration with Jamie Garside
and Neil Audsley from University of York. The paper proposes a memory interconnect for shared memory
architectures in many-core systems. A main architectural feature is that the interconnect is heavily pipelined enabling
it to be synthesized at high frequencies even with a large number of clients. Another highlight is that it has global arbitration
that can be programmed to behave like several different arbitration mechanisms, such as TDM, CCSP and FBSP.
The second paper "Retention Time Measurements and Modelling of Bit Error Rates of WIDE I/O DRAM in MPSoCs" was first-authored by our colleagues at Kaiserslautern University of Technology in collaboration with Sven Goossens from our Memory Team. This paper looks into the thermal behavior of 3D-stacked WIDE I/O DRAM and compares its impact on retention time and bit error rates to conventional 2D DRAM chips.
|2014-10-13 - Visiting Researcher at Airbus Group Innovations|
|Today, I start a two month stay as Visiting Researcher at Airbus Group Innovations in Ottobrunn, Germany. I will be working together with Jan Nowotsch on topics related to performance analysis of memory accesses in COTS multi-core platforms. During my stay, I look forward to meeting new people learning more about real-time systems in the avionics domain.|
|2014-10-11 - DRAMPower v4.0 Released!|
A new version of the DRAMPower tool has been released. The two main features of version 4 are:
|2014-10-03 - First PhD Student Graduates From the Memory Team|
Today, Karthik Chandrasekar was promoted to doctor as he confidently defended his PhD thesis
"High-Level Power Estimation and Optimization of DRAMs".
The thesis proposes a high-level power estimation tool called DRAMPower that estimates
the power and energy consumption of different generations of DRAMs based on a memory command trace and current values from the memory datasheet.
Since current numbers in datasheets are often pessimistic for a majority of the manufactured memory devices, a methodology is also proposed to
characterize DRAM modules post-manufacturing to achieve more accurate power and performance estimates for the characterized devices. Lastly,
the thesis discusses power optimization in the context of real-time memory controllers and proposes two power-down strategies to reduce the
power consumption of memories in real-time systems without sacrificing worst-case performance.
The defense went very well and the committee was particularly pleased with how the DRAMPower tool was verified using measurements on real hardware and how it has attracted interest from industry. Karthik is the first PhD student to graduate from the Memory Team and the rest of the team wishes him all the best for his future career at Nvidia.
|2014-08-19 - Article in ACM Transactions on Embedded Computing Systems (TECS)|
Manil Dev Gomony just had his first journal article accepted in ACM Transactions on Embedded Computing Systems.
The article is entitled
"A Real-Time Multi-Channel Memory Controller and Optimal Mapping of Memory Clients to Memory Channels" and is an
extension of his DATE paper from 2013, which was the first paper to provide architectures and techniques for multi-channel
memory controllers in real-time systems.
The two main contributions of the article are: 1) A configurable real-time multi-channel memory controller architecture with a novel method for logical-to-physical address translation. 2) Two design-time methods to map memory clients to the memory channels, one an optimal algorithm based on an integer programming formulation of the mapping problem, and the other a fast heuristic algorithm. The mapping algorithms are experimentally evaluated, showing benefits over two state-of-the-art mapping algorithms. Finally, a case study is presented that demonstrates how to configure a Wide IO DRAM in a High-Definition (HD) video and graphics processing system to emphasize the practical applicability and effectiveness of the work.
|2014-07-08 - Article in Real-Time Systems Journal has Appeared|
A journal article entitled
"Unified overhead-aware schedulability analysis for slot-based task-splitting"
has appeared in Real-Time Systems Journal. This article was first-authored by Paulo Baltarejo Sousa during my time at CISTER-ISEP Research Unit in Porto, Portugal
and is the result of a collaboration from that time.
The main contribution of the article is a unified scheduling theory for two state-of-the-art slot-based semi-partitioned algorithms, S-EKG and NPS-F. This new theory is based on exact schedulability tests, thus also overcoming many sources of pessimism in existing analyses. Another benefit of the proposed analysis is that it captures overheads, such as interrupts, context switches, and caches, occurring when tasks are deployed on real multi-core platforms. Together, these advantages results in a new efficient and reliable schedulability analysis for slot-based task-splitting algorithms.
|2014-05-20 - RTMemController v1.0 Released|
The Memory Team is proud to release another open-source tool to the community. This tool is called RTMemController and contains a mathematical formalization
of the dynamic command scheduler introduced in Yonghui Li's paper Dynamic Command Scheduling for Real-Time Memory Controllers
that will be presented at ECRTS. The tool is capable of determining worst-case and average-case execution times of memory transactions
of different transaction sizes and with varying degrees of bank interleaving.
An important driver for releasing this tool is to promote transparency and fair comparisons between work in the field. Longer term development plans for the tool may involve adding support for a memory controller front-end with different transaction schedulers, adding support for more memory generations (currently DDR3 is supported), and making the output compatible with DRAMPower to enable chaining the tools.
The official website of RTMemController is found here. Also check out the paper that describes the scheduling algorithm and its formalization.
|2014-03-28 - Paper Accepted at ECRTS|
|Today, we congratulate Yonghui Li on an accepted paper at ECRTS. The paper is entitled Dynamic Command Scheduling for Real-Time Memory Controllers and presents both an architecture and analysis for a dynamically scheduled SDRAM controller supporting different transaction sizes and memory map configurations. This is Yonghui's first accepted paper and we are proud to see that it got very good reviews from one of the most competitive conferences in the field. Now the work begins on preparing a camera-ready version and making the scheduling algorithm publicly available for comparisons in community.|
|2013-12-13 - Davit Mirzoyan Successfully Defends PhD Thesis!|
On this day, Davit Mirzoyan confidently defended his PhD thesis, earning the right
to call himself a doctor.
The thesis is entitled
Better than Worst-Case Design for Streaming Applications under Process Variation
and discusses how process variation during chip manufacturing can be exploited during
application mapping and voltage-frequency island partitioning to increase the number of
chips that satisfy the real-time requirements of the application. The work is very interesting,
as it captures how variation in transistor parameters affect application performance, thus tying
together the lowest and the highest levels of system design.
An interesting fact is that due to circumstances beyond Davits control, he had to write his thesis and send it off to the committee in only two months, something most people would not be able to do, yet he delivered a nice piece of work that was referred to as a 'very smooth read' by the committee. As Davits co-promotor, I am very proud of his achievement and I have very much enjoyed working with him during the past four years. I wish him the best of luck in his future career.
|2013-11-14 - DRAMPower v3.1 Released!|
The latest version of the tool now includes IO and
Termination power measures from Micron's DRAM Power Calculator for all
supported DRAM generations. This feature enables support for power
estimation of dual-rank DRAMs (DDR2/3/4). Additionally, new warning
messages have been added, to identify if the memory or bank state is
inconsistent in the user-defined command traces. This release also fixes
minor bugs related to Precharge All (PREA) to improve the accuracy of
DRAM power estimation.
Check it out here.
|2013-11-08 - Two Papers Accepted at DATE 2014|
Today we celebrate that the Memory Team had both papers submitted to
DATE accepted as full papers at the conference. The first paper was
written by Manil Dev Gomony and is entitled "Coupling TDM NoC and
DRAM Controller for Cost and Performance Optimization of Real-Time
Systems". This paper discusses area, power and performance benefits
of coupling the arbitration in a TDM NoC with the memory controller
arbitration, thereby reducing the number of arbitration points on the path
from processor to memory. The second paper entitled "Exploiting Expendable
Process-Margins in DRAMs for Run-Time Performance Optimization" was
first-authored by Karthik Chandrasekar. This paper shows how to
exploit excessive process margins in DRAMs
by proposing a methodology for how to determine the minimum
timings that a memory can safely run at, thereby improving performance.
|2013-11-01 - HiPEAC Membership|
|I have recently become a member of the HiPEAC Network of Excellence, a network with the goal to steer and increase the European research in the area of high-performance and embedded computing systems and to stimulate collaboration between academia and industry. Joining this network is an additional step towards establishing a strong international network and I look forward to meeting new interesting people as well as seeing some well-known faces at future HiPEAC events. The membership also provides interesting collaboration opportunities by providing collaboration grants to PhD students. Any PhD students interested in a three-month collaboration visit in Prague is welcome to contact me to discuss if there is any interesting work we can do together that can result in a high-quality joint publication.|
|2013-09-26 - Three Presentations at ESWEEK|
|The Embedded Systems Week kicks off next week in Montreal, Canada. Two of my students will be giving a total of three presentations, which may be interesting for those following my work. First, Sven Goossens will be presenting his CODES+ISSS paper "A Reconfigurable Real-Time SDRAM Controller for Mixed Time-Criticality Systems" on Monday September 30 10:30 - 11:00. On Thursday October 3, approximately, 09:50 - 10:10, he will also summarize all of his work on memory controllers for mixed time-criticality systems in an invited presentation entitled "A Mixed Time-Criticality SDRAM Controller" at the Memory Architecture and Organization Workshop (MeAOW). At almost the same time, October 3 10:00 - 10:30, Davit Mirzoyan will present his paper "Throughput Analysis and Voltage-Frequency Island Partitioning for Streaming Applications under Process Variation" at the Symposium on Embedded Systems for Real-Time Multimedia (ESTIMedia). We hope to see you there!|
|2013-09-10 - DRAMPower v3.0 Released!|
|DRAMPower v3.0 has been released! The tool can now be employed with two interfaces: (1) Command traces and (2) Transaction traces (new feature). To facilitate usage of memory transaction traces, DRAMPower now includes an optional DRAM command scheduler, which dynamically schedules and logs DRAM commands, corresponding to the incoming memory transactions, as if it was connected to a memory controller. The scheduler assumes a closed-page policy, employs FCFS scheduling across transactions and uses ASAP scheduling for DRAM commands. This release also adds support for DDR4 and LPDDR3 devices and fixes minor bugs to improve the accuracy of DRAM power estimation. Click here to check it out.|
|2013-08-13 - Research Overview Updated|
|The research overview was getting old and has now been updated to reflect the current state of my work. It also includes pointers to relevant papers on different topics. Click here to have a look.|
|2013-08-01 - New position at Czech Technical University in Prague|
|Today I start a new position as a Postdoctoral Researcher in the Department of Control Engineering at the Faculty of Electrical Engineering at the Czech Technical University in Prague. More specifically, I am in the Industrial Informatics group, led by Prof. Zdenek Hanzalek. Although a new country and a new workplace implies quite a change for me, little will change for those that I collaborate with. I will still do research on real-time systems and I will continue to supervise my students in Eindhoven and Porto. However, my research direction will change slightly within the scope of real-time systems to align with the interests of my new group and to make the most of my stay here.|
|2013-07-28 - Accepted Paper at ESTIMedia 2013|
|To our great delight, Davit Mirzoyan's paper "Throughput Analysis and Voltage-Frequency Island Partitioning for Streaming Applications under Process Variation" has been accepted at ESTIMedia 2013. The paper extends his earlier work and presents a framework to estimate the probability distribution of application throughput (e.g. frames per second in video decoding) in a system with Voltage-Frequency Island (VFI) partitions in the presence of process variation. The novelty of the framework lies in the computation of the probability distribution of throughput, based on a user-specified set of clock-frequency levels per VFI domain considering both within-die and die-to-die variations of cores. A methodology is furthermore provided to perform variation-aware partitioning of the cores of a MPSoC into VFIs for maximized timing yield (percentage of chips that satisfy a given throughput requirement).|
|2013-07-15 - Paper About CompSOC Tool-flow at FPGAworld 2013|
|A paper about the CompSOC tool-flow has been accepted that describes the highly automated effort of specifying and creating instances of the CompSOC platform, map applications to resources considering their real-time requirements, and executing the resulting system on FPGA. Three sub-flows of the tool-flow and their interactions are briefly explained: 1) the hardware tool flow, capable of translating a high-level description of a CompSOC platform instance into a fully synthesized implementation, 2) A system software flow, generating a software stack including a composable micro kernel, resource managers, drivers, and a virtual platform boot loader, and 3) An application flow that automatically generates a virtual platform configuration for applications that use the Cyclo-static Data Flow (CSDF) model of computation. The paper will be presented at FPGAworld and puts particular emphasis on practical aspects related to the first of these sub-flows and on the interaction with tools for our FPGA target.|
|2013-07-03 - Accepted Paper at CODES/ISSS 2013|
|Our paper "A Reconfigurable Real-Time SDRAM Controller for Mixed Time-Criticality Systems" has been accepted at CODES/ISSS 2013. The paper is first-authored by Sven Goossens and builds on the work of Jasper Kuijsten, a graduated master student from the Memory Team. In this paper, we present a new architecture of our real-time memory controller that supports predictable and composable run-time reconfiguration on use-case transitions, which allows trade-offs between guaranteed bandwidth, response time and power. It also presents a methodology for offering composable service to memory clients by means of composable memory patterns, an extension to our existing pattern-based approach. Lastly, a reconfigurable Time-Division Multiplexing (TDM) arbiter and an associated reconfiguration protocol are proposed. The TDM slot allocations can be changed at run time, while the predictable and composable performance guarantees offered to active memory clients are unaffected by the reconfiguration. The SDRAM controller has been implemented as a TLM-level SystemC model, and in synthesizable VHDL for use on an FPGA platform.|
|2013-06-11 - Invited Presentations in Northern, Southern, and Central Europe|
|The next two weeks involves quite a marketing effort, as I will give three invited presentations about real-time memory controllers in northern, southern, and central Europe, respectively. Tomorrow, I will present our work at the Faculty of Information Technology at Czech Technical University in Prague. On Friday, I will meet with Karl-Erik Arzen and Enrico Bini at the Department of Control at Lund's Institute of Technology and share my story. Lastly, next week Wednesday, I present at the ReTiS Lab at Scuola Superiore Sant'Anna. I thank all these institutes for the opportunity to present and I hope they will enjoy the story.|
|2013-06-10 - Paper Accepted at DSD 2013|
|Sahar Foroutan had a paper entitled "A General Framework for Average-Case Performance Analysis of Shared Resources" accepted at DSD 2013. This paper is a result of her six month collaboration visit in Eindhoven last year. The two main contributions of the paper are: 1) a general model for resource sharing based on queuing theory that can be used with different arbiters and that captures architectural features of the shared resource, such as pipelining and arbitration delay, and 2) three arbiter models for time-division multiplexing, static-priority arbitration, and round-robin, respectively, that assume general distributions (G/G/1) and fits within the framework.|
|2013-05-31 - Paper Accepted at RTCSA 2013|
Today, we congratulate Hazem Ali for having his first paper accepted at RTCSA.
The paper is entitled "Critical-Path-First Based Allocation of Real-Time Streaming Applications on 2D Mesh-Type Multi-Cores" and proposes
a mapping strategy for streaming applications, represented as acyclic data-flow graphs with throughput requirements, to multi-core architectures
under partitioned EDF scheduling. The key idea is to first map tasks on the critical-paths of the application to minimize their execution time and thereby
increasing the chance to satisfy the throughput constraint. The camera-ready version is available here.
Hazem Ali is a PhD student at the CISTER-ISEP Research Unit in Porto, supervised by Luis Miguel Pinho and myself, and this paper is a result of my six month visit there last year and the fruitful collaboration it has resulted in afterwards.
|2013-05-31 - DRAMPower v2.1 is Available and Variation-aware|
The DRAMPower tool has been updated to v2.1 with support for variation-aware power estimation for a selection of DDR3 memories,
based on the analysis presented in our DAC '13 article.
Towards this, 15 sample datasheets reflecting the impact of process-variations on DRAM currents have been added to tool.
For more information, or to download the tool, please refer to the official DRAMPower website.
|2013-05-16 - Article about Variation-aware Mapping Accepted by ACM TECS|
|ACM Transactions on Embedded Computing Systems (TECS) just accepted our article "Process-Variation Aware Mapping of Best-Effort and Real-Time Streaming Applications to MPSoCs". This work discusses how to efficiently map streaming applications, represented as synchronous data-flow graphs, with different types of real-time requirements to multi-processor systems affected by process variation (maximum frequencies of each processor follows a statistical distribution). The main goal is to map the tasks of the applications to the system in such a way that the probability of satisfying the real-time requirements of the applications is maximized. This work is an extension of the conference paper "Process-Variation Aware Mapping of Real-Time Streaming Applications to MPSoCs for Improved Yield", presented at ISQED in 2012. The camera-ready version is available here.|
|2013-04-17 - Paper Accepted at SIES 2013|
A paper entitled "Identifying the Sources of Unpredictability in COTS-based Multicore Systems" was accepted at SIES 2013.
This paper was written together with Dakshina Dasari, Vincent Nelis, Muhammad Ali Awan and Stefan Petters and is the first accepted
paper resulting from the six months I spent at the CISTER-ISEP Research Center in Porto. The contribution of the paper is a survey of sources
of unpredictability in commercial-of-the-shelf multi-core systems and the state-of-the-art research that is addressing them.
Update: The paper is now available online here.
|2013-03-26 - DRAMPower v2.0 Released!|
The new version of our tool for fast and accurate system-level power estimation of DRAMs has been released. This version features many important improvements,
such as significantly improved analysis speed (at least 10x), enabling analysis of much larger traces, as well as support for LPDDR/LPDDR2 and Wide I/O memories.
The results of this version have furthermore been verified by Kaiserslautern University of Technology using equivalent circuit-level SPICE simulations,
which established that the error of the tool is < 2% for all memory operations of any granularity for all memories supported by DRAMPower.
For more information, or to download the tool, please refer to the official DRAMPower website.
|2013-02-02 - Paper Accepted at DAC 2013|
For the second year in a row, Karthik Chandrasekar lands a paper at the prestigious Design Automation Conference (DAC).
The paper is entitled "Towards Variation-Aware System-Level Power Estimation of DRAMs: An Empirical Approach" and
discusses how to obtain more realistic power estimates with high-level power models by making them aware of
process variation. Just like his recently accepted DATE paper, this work is a result of a successful collaboration with Christian
Weis and Norbert Wehn at the University of Kaiserslautern.
Update: The paper is now available online. Click here to read it.
|2013-02-01 - Back in Eindhoven|
|After six great months at the CISTER Research Unit in Porto, I am back at Eindhoven University of Technology. I really enjoyed the opportunity to work in another group and learn more about traditional real-time systems and their applications. It has been great to get to know new people in the real-time community, both professionally and as friends. A few papers have already been submitted as a result of this collaboration and there are more to come over the next few months. To all my friends and colleagues in Porto, thank you very much and I look forward to stay in touch with you.|
|2013-01-08 - Jasper Kuijsten Graduates from the Memory Team|
|Another master student has graduated from the Memory Team. Jasper Kuijsten joined the team in March 2012 and has worked on predictable and composable reconfiguration of the memory controller front-end. His work has been very diverse and contains theoretical comparisons between different approaches to composability in terms of efficiency and reconfiguration effort, but also implementation of his concepts and ideas in both SystemC and VHDL. The Memory Team thanks Jasper for his hard work and good team spirit during the project and wishes him the best of luck in his future career.|
|2012-10-31 - Memory Team Scores Four out of Four Accepted Papers at DATE 2013!|
The preliminary author notification for DATE 2013 is now available on the conference
website and it reveals that the memory team scores an incredible four accepted papers
out of the four submitted, resulting in an acceptance ratio of 100% for the team!
The four paper titles are:
|2012-10-31 - Successful Collaboration Lands Paper at PADL 2013|
|Another successful collaboration has resulted in an accepted publication at the Fifteenth International Symposium on Practical Aspects of Declarative Languages (PADL). The title of the paper is "A Declarative Compositional Timing Analysis for Multicores Using the Latency-Rate Abstraction" and it was written together with Vitor Rodrigues, Simão Melo de Sousa, and Mário Florido from Universidade do Porto and Universidade da Beira Interior. The paper discusses the theory and declarative implementation of timing analysis for multi-cores using abstract interpretation. To manage the state-space explosion of possible interleavings of requests from different cores to shared resources, the latency-rate abstraction is proposed and proven to be sound in the context of the proposed analysis. The resulting loss of precision is then evaluated for a simple system where a memory is shared using TDM arbitration.|
|2012-08-07 - Paper Accepted at ESTIMedia 2012|
Andrew Nelson just had a paper "Power Versus Quality Trade-offs for Adaptive Real-Time Applications" accepted at
ESTIMedia 2012. The paper is based on the work of Sjoerd te Pas, one of my graduated master students, and discusses how
power consumption can be traded for application quality for adaptive real-time applications using existing DVFS techniques. The techniques
are demonstrated for an H.263 application on an FPGA instance of the CompSOC platform. Stay tuned for the camera-ready version.
Update: The paper is now available online. Click here to read it.
|2012-08-01 - Visiting Researcher at CISTER|
For the next six months, I am a visiting resarcher at CISTER
(Research Centre in Real-Time Computing Systems) based at the School of Engineering (ISEP) of the Polytechnic Institute of Porto (IPP), Portugal.
This gives me a great opportunity to work with some of the great minds in the real-time community, broaden my knowledge by exploring new applications
and research areas, as well as contribute with my experiences to the group. At this point, I am familiarizing myself with the work carried out in the
group and the work plan will be defined during the coming month.
Update: After settling in at CISTER, I am now working on two projects. The first one relates to their work on bus contention analysis, which is a familiar topic with a different twist. The second project is related to implementation and evaluation of scheduling algorithms in the Linux kernel, which is a completely new topic. Of course, I am also still spending time managing the work of the memory team in Eindhoven. Some new, some old, but in the end I am learning many new things both technically and culturally, and I am meeting many extraordinary people.
|2012-07-12 - Tutorial Accepted at HiPEAC 2013|
Our tutorial Designing Next-Generation Real-Time Streaming Systems was accepted at HiPEAC 2013,
which takes place in Berlin January 2013. The tutorial is a collaboration between Eindhoven University
of Technology, ST-Ericsson and
Saarland University, and presents, among other things, predictability concepts from the
CompSOC platform and its associated toolchain. We hope to see you there!
The tutorial webpage is available here.
|2012-07-06 - 5th Workshop on Compositional Theory and Technology for Real-Time Embedded Systems|
I have been appointed program co-chair of the on 5th Workshop Compositional Theory and Technology for Real-Time Embedded Systems
(CRTS 2012) together with Bjorn Andersson from the Software Engineering Institute at Carnegie Mellon University, USA. The workshop
is co-located with the Real-Time Systems Symposium (RTSS) in Puerto Rico and takes place on December 4th, 2012.
The goal of the workshop is to reduce the increasing design and analysis cost of real-time embedded systems by proposing
solutions based on compositional platforms and methodologies. These enable decomposition of a complex systems into components that can
be designed and analyzed in isolation and then integrated using interfaces with clearly defined temporal and functional properties.
We gladly invite you to submit contributions to the workshop or to participate during your stay at RTSS.
Click here to visit the workshop website.
|2012-05-15 - Paper Accepted at DSD 2012|
The memory team congratulates Gervin Thomas from TU Berlin for having
his paper entitled "A Predictor-based Power-Saving Policy for DRAM Memories"
accepted at DSD 2012. This work is the result of Gervin's HiPEAC collaboration visit in Eindhoven between
August and October 2011. During this time, he worked closely with Karthik Chandrasekar on finding a way to use
the self-refresh mode of DRAMs to reduce the power consumption in soft real-time systems without significantly reducing
performance. The camera-ready version of the paper will be available shortly.
Update: The paper is now available online. Click here to read it.
|2012-05-15 - Karthik Chandrasekar Receives HiPEAC Collaboration Grant|
|Today we celebrate that Karthik Chandrasekar has received a 3 month HiPEAC collaboration grant to visit the group of Prof. Norbert Wehn at Kaiserslautern Institute of Technology. The application process was competitive with approximately 30% of 67 proposals being funded. The grant serves to extend the existing collaboration between our two groups and will be used to conduct research on the hot topic of "Mobile and 3D-Stacked Wide I/O DRAM Power Modeling and Optimization".|
|2012-05-01 - New PhD Student on the Memory Team|
|The memory team welcomes Yonghui Li who just embarked on the four year quest towards a PhD degree in the context of the T-CREST project. We wish him the best of luck on this endeavor and look forward to working together.|
|2012-03-09 - CoMPSoC Website Launched - compsoc.eu|
The CoMPSoC project has launched an official website, www.compsoc.eu, with information about
the research, references to key publications, and links to the websites of the individual websites of the researchers. I recommend having a look
at this website, since it shows the system-level context, the bigger picture, of the memory controller research done by the memory team.
Update: The DATE demo is now posted on compsoc.eu for those that were unable to see it in Dresden.
Click here to enjoy the demo.
|2012-02-10 - Paper Accepted at DAC 2012|
Today we congratulate Karthik Chandrasekar on getting his paper
"Run-Time Power-Down Strategies for Real-Time SDRAM Memory Controllers"
accepted at Design Automation Conference (DAC) 2012, where it will be presented
in early June. The paper proposes two run-time power down strategies for real-time
SDRAM controllers that reduce power without sacrificing guaranteed bandwidth. One strategy
is conservative and saves power without affecting latency, whereas the second is more aggressive
and saves additional power at a slightly increased latency. The paper also
presents an algorithm to select the most energy-efficient power-down mode at run-time.
Update: The camera-ready version is now available. Click here to download it.